The present invention relates in general to a system control signal generator. More particularly, the invention relates to a signal generator employed in a computer or data processing system for providing timing signals, particularly, timing signals for controlling the system such as I/O and memory control signals.
In any type of a computer or data processing system, there is a bus controller that is employed for controlling signals transferred on the system bus. For example, one present bus controller that is employed is the Intel Model No. 8288. This device provides for effective bus control, but the problem associated therewith is that the device is relatively expensive and because of its universal design is unduly complex in configuration.
Accordingly, it is an object of the present invention to provide an improved system control signal generator or bus controller that is of improved construction particularly in that it can be fabricated less expensively.
Another object of the present invention is to provide an improved system control signal generator that is relatively simple in construction and that can use readily available inexpensive components without requiring special complex circuit design.
Still another object of the present invention is to provide an improved system control signal generator for use in a computer or data processing system and which requires a relatively small number of components for carrying out multiple controls and in which the signal generator is easy to maintain.
Another object of the present invention is to provide an improved system control signal generator that is of simplified construction, is thus less expensive, and which is readily adaptable to present overall computer system designs.